Our technologies address the most pressing challenges facing IC development teams for custom analog and digital, RTL synthesis, digital place and route, mixed-signal and system-on-chip (SoC) designs.
Calibre nmDRC and Calibre nmLVS are the market share leaders in physical verification. Calibre also leads the market with innovative features such as incremental DRC, which ensures you can complete your design rule checking quickly and efficiently, and equation-based design rules, which let designers define continuous, three-dimensional functions that accurately and precisely reflect the complex physical interactions of today’s nanometer designs.
Circuit Verification involves several essential steps in the design process that will help identify potential circuit or design errors as well as extract the necessary data for downstream circuit simulation. The layout is analyzed and compared vs. the schematic, the design is analyzed for short-term and long-term electrical failures and a detailed silicon model is constructed with intentional device, advanced parameters, and parasitic information to allow simulation to confirm the design meets electrical specifications (timing, power, etc.)
Mentor’s new Pyxis Custom IC Design Platform includes integrated solutions for design capture, floorplanning, custom routing, polygon editing, physical layout, schematic-driven layout, concurrent editing and chip assembly. To help companies jump-start their design cycles and cut time-to-market, Mentor Graphics and its foundry partners have developed design kits.
Mentor Graphics provides world-class analog/mixed-signal (AMS) verification solutions for transistor-level circuitry from the latest FinFET-based process nodes to traditional analog processes.
Innovative technologies for fast and high-quality design closure at advanced process nodes.
Mentor Graphics’ IC implementation solutions, Oasys-RTL™, Nitro-SoC™, Olympus-SoC™ and Calibre® InRoute, deliver solutions to the power, performance, capacity, time-to-market, and variability challenges of today’s digital IC designs.
Tanner AMS IC design flow SUpports analog/mixed-signal design in one highly-integrated, end-to-end flow. Engineers can perform top-down, mixed-signal simulation or co-simulation, synthesis with DFT support, place and route, and high-speed, “sign-off ready” timing analysis for tape-out, within one cost-effective, unified flow.